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Espressif Systems /ESP32 /LEDC /LSTIMER3_CONF

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Interpret as LSTIMER3_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DUTY_RES0DIV_NUM0 (PAUSE)PAUSE 0 (RST)RST 0 (TICK_SEL)TICK_SEL 0 (PARA_UP)PARA_UP

Fields

DUTY_RES

This register controls the range of the counter in low speed timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.
DIV_NUM

This register is used to configure parameter for divider in low speed timer0 the least significant eight bits represent the decimal part.
PAUSE

This bit is used to pause the counter in low speed timer0.
RST

This bit is used to reset low speed timer0 the counter will be 0 after reset.
TICK_SEL

This bit is used to choose slow_clk or ref_tick for low speed timer0. 1’b1:slow_clk 0:ref_tick
PARA_UP

Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data